The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Field-programmable gate arrays (FPGAs) are semiconductor devices comprising configurable logic blocks (CLBs) and programmable interconnections that interconnect the CLBs. The CLBs may be arranged in one or more arrays and can be programmed to perform functions of combinational and/or sequential logic. The programmable interconnections allow users to program connections between the CLBs. By programming CLBs and interconnections between the CLBs, users can configure an FPGA to perform complex logic functions. The CLBs and the programmable interconnections typically include memory that users can program. The memory may include static random access memory (SRAM). Since SRAM is volatile, the memory used in CLBs and programmable interconnections may need to be reprogrammed every time power is applied to the FPGA.
FIGS. 1A and 1B depict general components of a conventional FPGA 50. Referring to FIG. 1A, an exemplary layout of general components of the FPGA 50 in an integrated circuit (IC) is shown. The FPGA 50 may comprise at least one CLB array 100, at least one block RAM 52, a plurality of input-output blocks (IOBs) 54, a plurality of pins 56 of the IC, and at least one control module 58. To simplify discussion, a simplified functional block diagram of the FPGA 50 is shown in FIG. 1B-including, in particular, a CLB array 100, a block RAM 52, IOBs 54, and a control module 58.
The CLB array 100 may comprise a plurality of CLBs and programmable interconnections (not shown in FIGS. 1A and 1B). The block RAM 52 is an on-chip memory. The block RAM 52 may comprise several kilobits of RAM and may support dual-porting. The IOBs 54 may interface the components of the FPGA 50 to the pins 56 of the FPGA 50. Additionally, the IOBs 54 may interface the FPGA 50 to systems and devices that utilize the FPGA 50. The IOBs 54 may be arranged in banks, where each bank provides an interface that is based on an I/O standard. Thus, the FPGA 50 can communicate with devices that use the same or different interfaces. The control module 58 may generate clock signals that operate CLBs in the CLB array 100, the block RAM 52, and the IOBs 54. Additionally, the control module 58 may generate signals to address and program memory cells (not shown in FIGS. 1A and 1B), which are used to program the programmable interconnections.
Referring now to FIG. 2A, the CLB array 100 may comprise a plurality of CLBs 110 arranged in a matrix. Additionally, the CLB array 100 may comprise programmable interconnections that include connection switches C 120, routing switches S 130, and wiring segments 140. Each connection switch C 120 may connect an output of one CLB 110 to an input of another CLB 110. Additionally, the connection switches C 120 may connect inputs and/or outputs of the CLBs 110 to the wiring segments 140. Each routing switch S 130 may connect wiring segments 140 on one side of the routing switch S 130 to wiring segments 140 on other sides of the routing switch S 130. The wiring segments 140 may connect the CLBs 110 to the IOBs 54.
FIG. 2B shows one example of a conventional CLB 100 comprising multiple configurable logic elements (CLEs) 150-1, 150-2, . . . , 150-N (collectively CLEs 150), where N is an integer greater than or equal to 1. Each CLE 150 may be programmed to perform different logic functions. Each CLE 150 may receive a plurality of inputs of a given CLB 110. Each CLE 150 may generate one output depending on the programming of the CLE 150. Thus, each CLB 110 comprising N CLEs 150 may have N outputs.
Referring now to FIGS. 3A-3C, each CLE 150 may comprise one programmable logic element such as a lookup table (LUT) or a multiplexer. For example, in FIG. 3A, the CLE 150-1 may comprise a LUT 152. The LUT 152 may receive k inputs and may include a 2k-bit memory 153 as shown in FIG. 3B. The CLE 150-1 may perform a predetermined logic function depending on the programming of memory 153. For example, memory 153 can be programmed to perform a k-input AND gate, a k-input OR gate, etc. Depending on the states of the k inputs, a memory location in memory 153 is addressed. The LUT 152 generates an output f that is equal to the value of the bit programmed in the memory location addressed by the k inputs. The output f of the LUT 152 is latched by a D flip-flop 154. The output of the D-flip-flop 154 is output by a multiplexer 156 as an output (Output-1) of the CLE 150-1.
As shown in FIG. 3C, the CLE 150-2 may comprise a multiplexer 158 and memory 160. When the multiplexer 158 receives a set of inputs, the multiplexer 158 may generate an output (Output-2) based on the inputs and the bits programmed in memory 160. The CLE 150-2 may perform a predetermined logic function depending on the programming of memory 160. For example, the CLE 150-2 may function as a k-input AND gate when the multiplexer 158 receives k inputs and memory 160 is programmed as follows. The bits bit-1, bit-2, . . . , bit-N of the memory 160 may be programmed as 1, 0, . . . , 0, respectively, where N=2k. The output (Output-2) is equal to 1 only when all k inputs are 1, and the output-2 is 0 for all other states of the k inputs. In other words, the CLE 150-2 may function as a k-input AND gate when the memory 160 is programmed as above. As can be appreciated, the CLE 150-2 can perform other functions depending on the programming of memory 160.
Referring now to FIG. 4A, an example of programmable interconnections in the CLB array 100 is shown. A connection switch C 120-1 may communicate with a wiring segment 140-2 and may connect outputs of a CLB 110-1 to inputs of a CLB 110-2. A connection switch C 120-2 may communicate with a wiring segment 140-1 and may connect outputs of a CLB 110-3 to the inputs of the CLB 110-1.
As an example, the CLB 110-1 is shown to comprise three CLEs 150, namely, CLE-1 150-1, CLE-2 150-2, and CLE-3 150-3. The CLB 110-2 is also shown to comprise three CLEs 150, namely, CLE-1 150-4, CLE-2 150-5, and CLE-3 150-6. Similarly, the CLB 110-3 may comprise three CLEs 150 (not shown). Each of CLE-1 150-1, CLE-2 150-2, and CLE-3 150-3 receives three inputs and generates one output. Each of CLE-1 150-4, CLE-2 150-5, and CLE3 150-6 receives three inputs and generates one output. The inputs and outputs of the CLBs 110-1, 110-2, 110-3 may be buffered by line buffers 170.
Since each CLE 150 has three inputs and each CLB 110 has three outputs, each connection switch C 120-1, 120-2 is shown to comprise six pass-gate transistors (hereinafter transistors) and six memory cells M. For example, connection switch C 120-1 comprises transistors 122-1 through 122-6 (collectively transistors 122) and memory cells M 124-1 through 124-6 (collectively memory cells M 124). Each memory cell M 124 biases a gate of a corresponding transistor 122. Each transistor 122 is turned on or off depending on whether a corresponding memory cell M 124 is programmed to one of first and second states. The first and second states may be 1 and 0 (or 0 and 1), respectively. During programming, the control module 58 may generate signals that address and program the memory cells 124.
The connection switch C 120-1 may connect the outputs of the CLB 110-1 to the inputs of the CLB 110-2 as follows. The outputs of CLE-1 150-1, CLE-2 150-2, CLE-3 150-3 communicate with first ends (or terminals) of transistors 122-1, 122-2, 122-3, respectively. The inputs of CLE-1 150-4, CLE-2 150-5, CLE-3 150-6 communicate with first ends of transistors 122-4, 122-5, 122-6, respectively. The second ends of transistors 122 are connected to wires in the wiring segment 140-2 as shown.
When memory cells M 124-1, 124-6 are respectively programmed to turn on transistors 122-1, 122-6, the output of CLE-1 150-1 is connected to the inputs of CLE-1 150-4, CLE-2 150-5, and CLE-3 150-6. When memory cells M 124-2, 124-5 are respectively programmed to turn on transistors 122-2, 122-5, the output of CLE-2 150-2 is connected to the inputs of CLE-1 150-4, CLE-2 150-5, and CLE3 150-6. When memory cells M 124-3, 124-4 are respectively programmed to turn on transistors 122-3, 122-4, the output of CLE-3 150-3 is connected to the inputs of CLE-1 150-4, CLE-2 150-5, and CLE-3 150-6.
Additionally, a routing switch S 130-1 may route the outputs of the CLB 110-1 to the inputs of other CLBs 110, the IOBs 54, etc. via the wiring segments 140-2, 140-1. The routing switch S 130-1 may also route outputs of other CLBs 110, the IOBs 54, etc. to the inputs of CLB 110-2 via the wiring segments 140-2, 140-1. For example, the routing switch S 130-1 may route outputs of the CLB 110-3 to the inputs of the CLB 110-2 via the wiring segments 140-1, 140-2.
Specifically, the routing switch 130-1 may comprise a plurality of segment connection switches 132. The number of segment connection switches 132 may depend on the number of wires in the wiring segments 140-1, 140-2, which, in turn, may depend on the number of inputs and outputs of the CLBs 110. For example, since the CLBs 110-1, 110-2, 110-3 are shown to have three inputs and three outputs, the wiring segments 140-1,140-2 each comprises three wires. Accordingly, the routing switch 130-1 is shown to comprise a total of (3×3)=9 segment connection switches 132. Wires in the wiring segments 140-1, 140-2 may also be referred to as conductors of the wiring segments 140-1, 140-2.
Referring now to FIG. 4B, an exemplary schematic diagram of a segment connection switch 132 is shown. In particular, the segment connection switch 132 comprises six pass-gate transistors 134-1 through 134-6 (collectively transistors 134) and six memory cells M 136-1 through 136-6 (collectively memory cells M 136). Each memory cell M 136 biases the gate of a corresponding transistor 134. Each transistor 134 is turned on or off depending on whether the corresponding memory cell M 136 is programmed to one of first and second states. The first and second states may be 1 and 0 (or 0 and 1), respectively. During programming, the control module 58 may generate signals that address and program the memory cells 136.
Transistors 134 have may first and second ends (or terminals). Wires in the wiring segment 140-1 may have east (E) and west (W) ends. Wires in the wiring segment 140-2 may have north (N) and south (S) ends. The first ends of transistors 134-1, 134-6 and the second end of the transistor 134-2 may be connected to the east (E) end of a wire in the wiring segment 140-1. The second end of the transistor 134-1 and the first ends of transistors 134-4, 134-5 may be connected to the north (N) end of a wire in the wiring segment 140-2. The second ends of transistors 134-4, 134-6 and the first end of the transistor 134-3 may be connected to the west (W) end of the wire in the wiring segment 140-1. The second ends of transistors 134-3, 134-5 and the first end of the transistor 134-2 may be connected to the south (S) end of the wire in the wiring segment 140-2.
When memory cell M 136-1 is programmed to turn on transistor 134-1, the east (E) end of a wire in the wiring segment 140-1 is connected to the north (N) end of a wire in the wiring segment 140-2. When memory cell M 136-2 is programmed to turn on transistor 134-2, the east (E) end of the wire in the wiring segment 140-1 is connected to the south (S) end of the wire in the wiring segment 140-2.
When memory cell M 136-3 is programmed to turn on transistor 134-3, the south (S) end of the wire in the wiring segment 140-2 is connected to the west (W) end of a wire in the wiring segment 140-1. When memory cell M 136-4 is programmed to turn on transistor 134-4, the west (W) end of the wire in the wiring segment 140-1 is connected to the north (N) end of the wire in the wiring segment 140-2.
When memory cell M 136-5 is programmed to turn on transistor 134-5, the south (S) end of the wire in the wiring segment 140-2 is connected to the north (N) end of the wire in the wiring segment 140-2. When memory cell M 136-6 is programmed to turn on transistor 134-6, the east (E) end of the wire in the wiring segment 140-1 is connected to the west (W) end of the wire in the wiring segment 140-1. Depending on the connections provided by the connection switches C 120 and the routing switches S 130-1, outputs of any of the CLBs 110, IOBs 54, etc. may communicate with inputs of any of the CLBs 110, IOBs 54, etc.
FIGS. 5A and 5B illustrate an example SRAM memory cell 180 that is typically used in memory cells 124 and 136. As shown in FIG. 5A, the SRAM memory cell 180 comprises six transistors T1 through T6. Transistors T3 through T6 form two cross-coupled inverters that store a 0 or a 1. Transistors T1 and T2 are called access transistors and control access to the SRAM memory cell 180. In FIG. 5B, a simplified schematic of the SRAM memory cell 180 comprising the cross-coupled inverters and the access transistors is shown.
Access to the SRAM memory cell 180 is controlled by a word line (WL) that controls the access transistors T1 and T2. By turning the access transistors on or off, the word line WL controls whether the SRAM memory cell 180 is connected to bit lines BL and BL′ during read/write operations. The bit lines BL and BL′ transfer data to and from the SRAM memory cell 180 during write and read operations. The control module 58 generates the signals to write/read data to/from the SRAM memory cell 180.
Specifically, during a write operation, the bit lines BL and BL′ are set to a data value (e.g., a 0 or a 1) that is to be stored in the SRAM memory cell 180. If a 0 is to be written, BL is set to 0 and BL′ is set to 1. Conversely, a 1 is written by inverting the data values of the bit lines BL and BL′. Setting the word line WL high (i.e., setting WL=1) latches the data present on the bit lines BL and BL′ into the cross-coupled inverters in the SRAM memory cell 180. During a read operation, both the bit lines BL and BL′ are initially pre-charged to a 1. The word line WL is set high, which turns on the access transistors T1 and T2, and data stored in the cross-coupled inverters is transferred to bit lines BL and BL′.